FEATURES ■ 4 – 512K x 8 SRAMs & 4 – 512K x 8 Flash Die in One MCM ■ Access Times of 25ns, 35ns (SRAM) and 60ns, 70ns, 90ns (Flash) ■ Organized as 512K x 32 of SRAM and 512K x 32 of Flash Memory with Common Data Bus ■ Low Power CMOS ■ Input and Output TTL Compatible Design ■ MIL-PRF-38534 Compliant MCMs Available ■ Decoupling Capacitors and Multiple Grounds for Low Noise ■ Commercial, Industrial and Military Temperature Ranges ■ Industry Standard Pinouts ■ TTL Compatible Inputs and Outputs ■ Packaging – Hermetic Ceramic ● 66–Lead, PGA-Type, 1.385"SQ x 0.245"max, Aeroflex code# "P1,P5 with/without shoulders)" ● 68–Lead, Dual-Cavity CQFP(F2), 0.88"SQ x .20"max (.18 max thickness available, contact factory for details) (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint) FLASH MEMORY FEATURES ■ Sector Architecture (Each Die) ● 8 Equal Sectors of 64K bytes each ● Any combination of sectors can be erased with one command sequence ■ +5V Programing, +5V Supply ■ Embedded Erase and Program Algorithms ■ Hardware and Software Write Protection ■ Page Program Operation and Internal Program Control Time. ■ 10,000 Erase/Program Cycles
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